ASIC Datasheet - Digital Core Design

2016
DEEPROM IP Core
Serial EEPROM Controller v. 1.01
COMPANY OVERVIEW
Digital Core Design is a leading IP Core provider
and a System-on-Chip design house. The company
was founded in 1999 and since the very beginning
has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers
and with more than 500 hundred licenses sold to
companies like Intel, Siemens, Philips, General
Electric, Sony and Toyota. Based on more than 70
different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we
are designing solutions tailored to your needs.
IP CORE OVERVIEW
The DEEPROM Controller performs communication
and exchanges data between external serial
EEPROM Memory and CPU’s external memory
interface. The serial EEPROM contents are accessible to the CPU in the same manner as a common
SRAM memory, but require READY input to expand
time access. The Core is designed to work with
popular 25XXX SPI Serial EEPROMs (eg Microchip).
APPLICATIONS
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Synthesis scripts
Example application
Technical support
● IP Core implementation support
● 3 months maintenance
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LICENSING
Comprehensible and clearly defined licensing
methods without royalty-per-chip fees make use
of our IP Cores easy and simple.
Single-Site license option – dedicated to small and
middle sized companies, which run their business
in one place.
Multi-Site license option – dedicated to corporate
customers, who operate at several locations. The
licensed product can be used in selected company
branches.
In all cases the number of IP Core instantiations
within a project and the number of manufactured
chips are unlimited. The license is royalty-per-chip
free. There are no restrictions regarding the time
of use.
There are two formats of the delivered IP Core:
VHDL or Verilog RTL synthesizable source code
called HDL Source code
Connection of Serial EEPROM to CPU
Non-volatile data storing
FPGA EDIF/NGO/NGD/QXP/VQM called Netlist
KEY FEATURES
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Standard memory interface with ready control
Configurable SPI parameters
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Serial clock prescaler
SPI mode
CS hold/setup
Updating bits in EEPROM status register
Simple interface allows easy connection
to microcontrollers
Fully synthesizable, static design with no internal
tri-states
Synchronous design with positive edge clocking
and synchronous reset
No internal tri-states
Scan Test ready
DELIVERABLES
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Source code:
● VHDL Source Code or/and
● VERILOG Source Code or/and
● Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment
● Active-HDL automatic simulation macros
● ModelSim automatic simulation macros
● Tests with reference responses
Technical documentation
● Installation notes
● HDL core specification
● Datasheet
Delivery of the IP Core and documentation updates, minor
and major versions changes
Phone & email support
PINS DESCRIPTION
SPI Interface – Controls serial data transmission
based on SPI protocol.
Control Unit– Performs main control. Generates
commands and data sequences for serial EEPROM
device management
CPU Interface – Controls access from CPU and generates ready signal control.
PINS DESCRIPTION
PIN
TYPE
rst
datai(7:0)
addr(15:0)
cs
rd
wr
esi
datao(7:0)
ready
eso
esck
ecs
input
input
input
input
input
input
input
output
output
output
output
output
DESCRIPTION
Global reset
CPU data bus (input)
CPU address lines
Chip select
CPU read strobe
CPU write strobe
Serial data input
CPU data bus (input)
Data ready control
Serial data output
Serial clock
Serial device chip select
1
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
TYPICAL DEEPROM CONNECTION
The figure below shows typical connection of DEEPROM Controller to microprocessor and serial EEPROM
memory.
datao
datai
datai
datao
address
CPU
ready
rd
wr
addr
busy
rd
DEEPROM
controller
wr
eso
esi
esi
eso
esck
esck
ecs
ecs
hold
hold
wp
rst
clk
Serial
EEPROM
wp
cs
clk
PLL
CONTACT
BLOCK DIAGRAM
Digital Core Design Headquarters:
Wroclawska 94, 41-902 Bytom, POLAND
clk
rst
EEPROM
Interface
datai
datao
addr
wr
rd
cs
ready
esi
eso
esck
ecs
e-mail:
tel.:
fax:
[email protected]
0048 32 282 82 66
0048 32 282 74 37
Distributors:
CPU
Interface
Please check:
http://dcd.pl/sales
Control Unit
2
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.